Conventionally, a verification using a logical simulation has been conducted for a designed circuit. For the verification of the designed circuit, verification items are determined. Next, a priority of the verification items (an order to perform priority items) is defined. A scenario is created to instruct a logical simulation pattern in accordance with the priority of the verification items, and the logical simulation is executed.
The priority of the verification items is defined based on “items strongly recommended to verify”. Especially, the “items strongly recommended to verify” correspond to items for verifying portions which may include bugs, or portions which may broadly influence other logics (logic circuits) due to modification of Register Transfer Level (RTL) when a bug is found.
Also, in general, when the bug is found by the verification using the logical simulation and the RTL is modified for the bug, the verification is performed again, in order to confirm modification contents and to confirm how the modification influences peripheral logics. In this re-verification, verification items, which activate a modified logic of the RTL, are also considered as the “items strongly recommended to verify”.
In light of extracting portions which the modification influences, a method is considered in which a result output of an initial logical simulation is read out, and a cell where an error occurs in a circuit and a cell of a post-stage which is influenced by an output signal of the cell are determined. Another method may be considered in which by setting a register or an external output pin as a start point in a cell within circuit connection information after a circuit is modified, connection information of cells in the circuit connection information is traced back until reaching a register or an external input pin.
Also, regarding the priority for conducting the verification, a few technologies are proposed. In one technology, a signal transition confirmation verification is conducted with respect to a verification target portion in a circuit, verification test patterns or verification target portions are prioritized depending on a ratio of a signal transition, and the verification is conducted in an order based on the priority. In another technology, regarding an influence level for an operation of a logical circuit when an input signal is changed, a priority is defined for an input signal input into a logical circuit being a verification target.